This invention relates to methods of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect power transistor (commonly termed a xe2x80x9cMOSFETxe2x80x9d) or an insulated-gate bipolar transistor (commonly termed an xe2x80x9cIGBTxe2x80x9d). The invention also relates to semiconductor devices manufactured by such a method.
Such trench-gate semiconductor devices are known having source and drain regions of a first conductivity type separated by a channel-accommodating body region of the opposite second conductivity type. An advantageous method of manufacture is disclosed in U.S. Pat. No. 5,378,655 (our reference PHB 33836), in which the formation of the source region is self-aligned with the trench (termed xe2x80x9cgroovexe2x80x9d) which comprises the gate. This self-alignment is achieved by the disclosed and taught method summarised as follows. A trench is etched through a window in a mask on a semiconductor body. After removing the mask, gate material is provided in the trench and then an upper portion of the gate material is oxidised to form a trench-gate structure which has an insulating cap on the gate. The insulating cap is then caused to form a step which protrudes from the adjacent semiconductor surface. A layer is then provided over the surface structure and then etched to leave a side wall spacer in the trench-gate step. The spacer is then used to define the source region which is thus formed to be self-aligned to the trench-gate structure.
The whole contents of U.S. Pat. No. 5,378,655 are hereby incorporated herein as reference material. By using such techniques as disclosed in U.S. Pat. No. 5,378,655, the number of photolithographic masking steps which require separate alignment can be reduced and compact cellular device structures can be formed.
Trench-gate semiconductor devices are also known in which the channel-accommodating body region is of the same, first conductivity type as the source and drain regions. In this case, the conductive channel is formed by charge-carrier accumulation by means of the trench-gate. Similar considerations arise with respect to the doping of the regions and the etching of the trench, as in the more usual device in which the channel-accommodating region is of the opposite, second conductivity type.
It is an aim of the present invention to modify the manufacture of trench-gate semiconductor devices so as to permit the use of a side wall spacer at the trench-gate structure for self-aligned formation of the source region while providing a simpler process with better definition of the source region.
According to the present invention there is provided a method of manufacture in which gate material is provided in a trench with a trench etchant mask still present so that the gate material forms a protruding step from the adjacent surface of the semiconductor body, a side wall spacer is formed in the step to replace the mask and the source region is formed with a lateral extent determined by the spacer, and then the gate is provided with an insulating overlayer.
The method as set out in claim 1 includes quite different steps (a) to (g) from the method steps of U.S. Pat. No. 5,378,655. In particular the side wall spacer is formed in the step in the trench gate structure at a stage before providing the gate with an insulating overlayer. The advantage is that the trench-gate structure at this early stage has a better defined edge provided by the gate material than the edge provided later by the oxidised gate insulating cap in the method of U.S. Pat. No. 5,378,655. As a result the lateral extent of the source region is better defined and so is the area over which the source electrode contacts the source region and the channel-accommodating body region.
Various preferred features in accordance with the invention are set out in claims 2 to 9. In one preferred feature formation of the side wall spacer may be achieved by removing the mask, then covering the protruding step of the gate material and the adjacent semiconductor body surface and then etching the covering material to leave the spacer. In another preferred feature, after formation of the source region, a dielectric cover may be provided beside the spacer to the top of the spacer, selective etching of the gate material leaves a gate top surface below the top of the spacer, the gate insulating overlayer is provided on the gate top surface and then the dielectric cover is removed. Alternatively, when the gate material is silicon, the insulating overlayer may be provided by oxidising an upper part of the gate material. In a preferred such oxidation method for forming the insulating overlayer, where the semiconductor body is monocrystalline silicon, the spacer is silicon dioxide and the gate material is doped polycrystalline silicon, different rates of oxidation produce thin and thick oxide layers respectively in the mono- and poly-crystalline silicon and the thin oxide layer is then removed to leave some of the thick oxide layer as the gate insulating overlayer. In another preferred feature three doped layers are initially provided in a starting semiconductor body with the source region and the channel-accommodating body region to be formed from the top two layers. After formation of the side wall spacer, the source region may be formed by etching through the top layer except where masked by the spacer and the layer underneath may be partly etched to provide a side surface of the body region also under the spacer.